Silicon Memory

What is error checking and correction? page 2/2

Now let’s move up to a module that is intended for a data bus 64 bits wide. For an architecture with no error checking, the layout is the same as in the other cases, with the exception that we use even denser chips capable of storing 8 bits at a time:

If we wish to use the parity feature as before, then we need another 8 bits just for the parity alone, as we need one parity bit for every eight data bits. Thus we need to read and write a total of 72 bits: 64 for our data, and 8 for the parity data. As you can see, things are getting a little sizeable at this stage.

There are other, better ways of error checking. Using an algorithm, a value is computed for each byte; it might be a simple checksum or something more comprehensive. This is commonly called ECC, or Error Checking and Correction.
There are two implementations of this as far as how we build this into the hardware. In one case, the ECC is done by an "engine", which takes the form of a dedicated chip mounted on the module along with the other memory chips. The ECC engine chip’s job is to calculate and store ECC information when the memory is being written to, as well as check this same information when the memory is being read. This removes the responsibility from the computer system – the error correction is carried out by the memory module itself and so this process becomes transparent.

The other way is to have the computer be the "engine": the system works out the ECC data for each read or write.

ECC requires 8 bits clear in order to function. This 8-bit working space can be implemented in a couple of ways: the memory module itself might have a separate 8-bit data path reserved exclusively for ECC use, or two parity-type memory modules, each having 4 parity bits available, could be cascaded in order to provide the required 8 bits.

Now let's take a look at how a standard memory module with parity can function as an ECC module. As you recall, if we take a module of width 36 bits, 32 of those are for data and 4 are for the parity check bits. We can use a pair of these modules together to implement ECC – in this case we have a total width of 72 bits: 64 for the actual data, and the remaining 8 for the ECC data. Remember that whether we're using parity or ECC, we need a separate bus to store this error-checking information. By putting two of these 36-bit modules together in this fashion, we are making a total of 8 bits available to the computer system for storing 'error' information. We need 8 bits to implement ECC, so for motherboards which use the Intel chipset, and where the manufacturer of that motherboard has decided to make this feature available, a pair of modules can be utilised in ECC mode.

The newer families of chipsets available on the market today are very versatile. These can implement either parity or ECC operation as required.

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					What is error checking and correction? page 2/2
					What is error checking and correction? page 2/2
					Now let’s move up to a module that is intended for a data bus 64 bits wide. For an architecture with no error checking, the layout is the same as in the other cases, with the exception that we use even denser chips capable of storing 8 bits at a time:




					If we wish to use the parity feature as before, then we need another 8 bits just for the parity alone, as we need one parity bit for every eight data bits. Thus we need to read and write a total of 72 bits: 64 for our data, and 8 for the parity data. As you can see, things are getting a little sizeable at this stage.


					There are other, better ways of error checking. Using an algorithm, a value is computed for each byte; it might be a simple checksum or something more comprehensive. This is commonly called ECC, or Error Checking and Correction. There are two implementations of this as far as how we build this into the hardware. In one case, the ECC is done by an "engine", which takes the form of a dedicated chip mounted on the module along with the other memory chips. The ECC engine chip’s job is to calculate and store ECC information when the memory is being written to, as well as check this same information when the memory is being read. This removes the responsibility from the computer system – the error correction is carried out by the memory module itself and so this process becomes transparent. The other way is to have the computer be the "engine": the system works out the ECC data for each read or write. ECC requires 8 bits clear in order to function. This 8-bit working space can be implemented in a couple of ways: the memory module itself might have a separate 8-bit data path reserved exclusively for ECC use, or two parity-type memory modules, each having 4 parity bits available, could be cascaded in order to provide the required 8 bits. Now let's take a look at how a standard memory module with parity can function as an ECC module. As you recall, if we take a module of width 36 bits, 32 of those are for data and 4 are for the parity check bits. We can use a pair of these modules together to implement ECC – in this case we have a total width of 72 bits: 64 for the actual data, and the remaining 8 for the ECC data. Remember that whether we're using parity or ECC, we need a separate bus to store this error-checking information. By putting two of these 36-bit modules together in this fashion, we are making a total of 8 bits available to the computer system for storing 'error' information. We need 8 bits to implement ECC, so for motherboards which use the Intel chipset, and where the manufacturer of that motherboard has decided to make this feature available, a pair of modules can be utilised in ECC mode. The newer families of chipsets available on the market today are very versatile. These can implement either parity or ECC operation as required.

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