What is error checking and correction? page 1/2
					Although we have just seen that parity checking allows us to be aware that an error has occurred in our data, it is far from perfect. Remember that the parity check merely tells us that the number of "1s" in a data byte is an odd or an even number – if we have a byte that satisfies the odd parity criterion, and a "1" appears or disappears due to an error, then we are aware that an error has occurred, If, however, we have TWO instances, then the "oddness" or the "evenness" is preserved; the data is corrupt, but we are unaware of it, as it still satisfies the parity rule. In other words, we need something far more robust to cope with the millions of bytes transferred every minute in a computer system. You’ll recall our original data bus of 8 bits. A typical 30-pin memory module would look like the following, having 8 chips, with each chip storing data in one "lane" of the data highway:
					If we wanted to store parity as well, then we need the ninth lane. This often appears as a ninth chip on the module, and operates in exactly the same fashion as the other eight:
					Now let’s look at what we need for a personal computer system which has a data bus of 32 bits in width. Obviously a memory module for this architecture will have to accommodate four times as many bits; different chips of greater density are used to store 4 bits at a time, so a typical memory module has 72 pins:
					As you can see, each chip is responsible for storing four bits of data. If we need to add parity checking, then we need an additional four bits, since in our first look at parity we needed one extra bit for every eight. So all together the memory module must be 36 bits wide: 32 for the data, and 4 for the parity bits. To obtain the extra four bits, we can either add another chip of 4 bits width, or four separate chips of 1 bit each. The exact implementation does not matter, as long as we still manage to read and write 36 bits:
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